By Eric A. Vittoz (auth.), Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing (eds.)
The cognizance of sign sampling and quantization at excessive pattern charges with low energy dissipation is a vital target in lots of purposes, includ ing transportable video units reminiscent of camcorders, own conversation units equivalent to instant LAN transceivers, within the learn channels of magnetic garage units utilizing electronic information detection, and so on. This paper describes structure and circuit techniques for the layout of high-speed, low-power pipeline analog-to-digital converters in CMOS. the following the time period excessive pace is taken to suggest sampling premiums above 1 Mhz. within the first part the dif ferent conversion suggestions acceptable during this diversity of pattern premiums is dis stubborn. Following that the actual difficulties linked to strength minimization in video-rate pipeline ADCs is mentioned. those contain optimi zation of capacitor sizes, layout of low-voltage transmission gates, and opti mization of switched capacitor achieve blocks and operational amplifiers for minimal energy dissipation. for example of the applying of those tech niques, the layout of a power-optimized lO-bit pipeline relief converter (ADC) that achieves =1. sixty seven mW in line with MS/s of sampling expense from 1 MS/s to twenty MS/s is defined. 2. innovations for CMOS Video-Rate reduction Conversion Analog-to-digital conversion thoughts will be classified in lots of methods. One handy technique of evaluating thoughts is to ascertain the variety of "analog clock cycles" required to provide one powerful output pattern of the sign being quantized.
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Additional info for Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power
The current gain of a single bipolar stage can be improved by using Darlington or Widlar types of structures. The voltage gain of a MOS stage can be increased by applying cascodes to the circuit. In BiCMOS technology, the gain can be improved by combining the high current gain of a MOS transistor and the large transconductance of a bipolar transistor. 47 References [I] G. D. Thesis, Delft University of Technology, Delft, The Netherlands, 1992. H. I. d. S. Appl. No. 4,555,673, Nov. 26,1985. H. Huijsing and D.
At resolutions in the 8-12 bit range, the only practical options for low power dissipation are multistep flash and pipeline configurations. Multistep flash implementations have been used very successfully in low-power applications at the to-bit level . Pipelines are also attractive  and have the potential advantages of inherent single-path sampling of the signal, giving good high-frequency effective bit performance, and the capability of using non-critical purely dynamic comparators because of the amplification of the signal in the pipeline coupled with the use of digital correction.
Therefore the sum of the base-emitter voltages of the output transistors is approximately constant. 9 V. Drawbacks of this circuit are the relatively large loss of signal current in the resistors and a quiescent current in the output transistors which is determined by inaccurate resistors. One problem can be overcome by directing the signal current through cascodes, Q] and Q2, to the complementary output transistor which results in a higher gain, as is shown in Fig. 21. The inaccurate biasing due to the large resistors, however, remains.