By Ricardo Martins, Nuno Lourenço, Nuno Horta
This ebook introduces readers to a number of instruments for analog format layout automation. After discussing the situation and routing challenge in digital layout automation (EDA), the authors assessment quite a few automated structure iteration instruments, in addition to the latest advances in analog layout-aware circuit sizing. The dialogue comprises diversified tools for computerized placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The suggestions and algorithms of all of the modules are completely defined, permitting readers to breed the methodologies, increase the standard in their designs, or use them as start line for a brand new software. all of the equipment defined are utilized to functional examples for a 130nm layout strategy, in addition to placement and routing benchmark sets.
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Extra resources for Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques
The few commercial tools overviewed show that only the user-assisted approaches, that offer control over the generation, found their way into the EDA market. These tools are used to speed up the manual design task by means of interactive functionalities. Most of the available commercial solutions stand out because of the powerful GUIs provided and their characteristics as layout project managers, but lacking on the algorithmic complexity for the automatic generation. At the same time, the reviewed automation approaches are usually limited to some specific circuit or circuit class, and the large time required to create a new tool or prepare an existing one to support a new circuit, causes analog designers to keep on designing the layout manually.
The model was developed for the aluminum conductors used during the early years of integration industry. 5) where, A is a constant that contains a factor involving the cross-sectional area of the interconnect, J the current-density in amperes per square centimeter, Φ the activation energy in electron volts for the interconnect material, k the Boltzmann constant, T the working temperature of the interconnect, and n is used as a scaling factor. By observing Eq. 2 Routing 23 and the temperature, which may be indirectly controlled by assigning power and thermally-sensitive devices and interconnects in different areas of the chip, and by considering worst-case conditions in the determination of the current-densities.
4 Closing the Gap Between Electrical and Physical Design The post-layout performance of a circuit needs to be guaranteed in the presence of layout parasitics, which prevent the circuit from reaching the expected performance values. 5, need to be avoided as much as possible . , an upper limit in the layout width, causing expensive redesigns. One possible solution involves the overlap of these two different phases, by including layout-induced effects into the circuit sizing phase, which is overviewed in the next sub-section.